1. Field of the Invention
The present invention relates to a semiconductor inspection system for analyzing patterns on a semiconductor wafer by use of design data. More specifically, the present invention relates to a semiconductor inspection system provided with a system configuration for automatically generating conditions for capturing and inspection of patterns out of the design data, as well as a method of stably performing a matching process between the design data and scanning electron microscope (SEM) images.
2. Background Art
In recent years, there is a production shift in the semiconductor industry from production of memory chips to production of system large scale integrated circuits (LSIs). From a viewpoint of patterns on a semiconductor wafer, unlike patterns of a memory chip, patterns of a system LSI are not designed as simply repeated patterns. Accordingly, in the case of performing pattern measurement of the system LSI with a length-measuring SEM, which is one of the semiconductor evaluation systems, templates for measuring positions, in other words, templates for matching need to be frequently changed. In actual measurement, frequent capturing operations for registration of the templates may incur a considerable decline in entire throughput. Accordingly, generation of the templates directly from existing design data such as computer aided design (CAD) data has been requested. In the meantime, a wafer size is increased up to 300 mm, whereby the wafer cannot be conveyed by manpower. In addition, inspection in a high-purity clean room is becoming essential. Therefore, complete robotization has been desired in a semiconductor facility. Accordingly, an operator-free and fully-automated semiconductor inspection system is requested, which is not arranged to generate only the templates for measuring positions but is also arranged to generate all conditions required for inspection including capturing conditions, points for length measurement and length-measuring algorithms out of the design data, whereby actual inspection is performed under the foregoing conditions.
In a conventional length-measuring SEM, an image of an actual wafer is captured first and the image is used for registration of the points for image recognition, the positions for length measurement and the length-measuring algorithms. In other words, the actual wafer is required in the first place, and it is also necessary to occupy the length-measuring SEM temporarily to perform capturing of SEM images and registration of various conditions. Moreover, since technologies for matching design data with SEM images have not been developed adequately, accurate matching has been difficult to do. For example, in the case of specifying a pattern position on a SEM image of a semiconductor wafer by applying the design data to a template with the conventional technology, the SEM image is filtered with a Sobel filter or the like to detect edge components for generating an edge image, and then matching such as a normalized correlation process between the edge image and the design data is performed.
FIG. 1 shows a schematic flowchart of conventional processes and FIG. 7 shows some image examples used in the conventional processes. First in Step 101, registration of a template of a desired pattern is performed by use of the design data. The pattern registered from the design data is shown as an image 701. Next, a SEM image is obtained in Step 102. The obtained SEM image is shown as an image 702. In Step 103, the obtained SEM image is subjected to edge emphasis filtering with a Sobel filter or the like. In Step 104, the edge-emphasized image is converted into binary codes for generating a line image in which the edge is only extracted. An image 703 shows the line image extracted out of the SEM image 702. In Step 105, a matching process such as normalized correlation is performed between the line image and the design image registered in Step 101. Then, position detection is performed in Step 106. When detection is performed a plurality of times, Step 102 to 107 will be iterated.
In a conventional semiconductor inspection system, registration of points for image recognition, positions for length measurement and length-measuring algorithms have been performed once after capturing an image of an actual wafer and by use of the image. For this reason, there has been a problem that throughput is not improved because registration is time-consuming and the system is occupied at the time of registration. Moreover, there has been a problem that it is impossible to construct an operator-free and fully automated semiconductor inspection system because the conventional system always requires an operator for judgment and registration by observation of actual SEM images. Furthermore, concerning the technology for matching design information with the SEM images, the conventional technology cannot respond to deformation between the CAD data and the SEM images. The conventional technology also has a problem in the event of extracting edge information out of the SEM image that the edge information cannot be adequately extracted due to a signal/noise ratio (an S/N ratio) of the image. In the event of generating a line image by conversion into binary codes, the conventional technology would be incapable of obtaining an optimum value for a threshold, because determination thereof has been difficult. Accordingly, there has been a problem that a correlation coefficient becomes considerably small in the subsequent matching process by normalized correlation.